Exemplary embodiments of the present invention relate to semiconductor memory devices, and more particularly, to a device and method for storing error information in a memory device, which is applicable to any semiconductor memory chip.
In the early stage of the memory semiconductor industry, a larger number of original good dies, which had no defective cell in a memory chip that passed through a semiconductor fabrication process, were distributed on a wafer. However, as the memory capacity has increased, it has become difficult to fabricate a memory chip without a defective cell. At the present time, there is a small chance that a memory chip will be fabricated without a defective cell.
In order to overcome this limitation, a method for replacing a defective memory cell with a spare memory cell (i.e., a redundancy memory cell) has been proposed. In order to replace a defective memory cell with a redundancy memory cell, a solution thereof must be calculated by using external equipment. Research is being conducted to install such a repair circuit (i.e., a memory self-repair circuit) in a memory chip.
Three main parameters to be considered for a memory self-repair circuit may be an area, a repair rate, and an analysis speed of a repair circuit. The area is a parameter connected directly with the semiconductor chip fabrication cost. The repair rate is an important parameter connected with the yield of a semiconductor device. The analysis speed of a repair circuit may also be regarded as a parameter connected directly with the semiconductor chip fabrication cost, because it is proportional to a test time.
A repair most method is disclosed in the prior art (e.g., M. Tarr, D. Boudreau, and R. Murphy, “Defect analysis system speeds test and repair of redundant memories”, Electronics, vol. 57, pp. 175-179, Jan. 12, 1984). A repair most method stores the number of defective cells of each row/column address detected during a test process, compares the number of defective cells of each row/column address after completion of the test process, and replaces a defective memory cell with a redundancy memory cell in descending order of the number of defects at an address. However, the repair most method of the prior art utilizes a large area because it requires a large-capacity buffer for storing a defective bit map. Also, the repair most method of the prior art may have a long defect analysis/repair time because it can perform a defect repair operation only after completion of a test process.
A local repair most method is also disclosed in the prior art (e.g., C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in Redundancy Analysis for Memory Yield Improvement”, IEEE Trans. Reliability, vol. 52, pp. 386-399, December 2003). The local repair most method of the prior art uses a small-sized defect bit map to reduce the area while applying a method similar to the repair most method. However, the local repair most method of the prior art cannot store all information for efficient repairs due to a small-sized bit map, and cannot repair more than a predetermined number of defects due to insufficient information stored (i.e., cannot repair defects due to insufficient information even in the case of sufficient redundancy memory), thus reducing the repair rate.
Also, an essential spare pivot method has been disclosed. The essential spare pivot method stores only core defect addresses instead of a defect bit map in order to reduce the area. Therefore, a defect address collecting process is performed during a test process, thus improving the analysis speed of a self-test circuit. However, a register capacity for storing defect addresses is insufficient, thus reducing the repair rate.